US 12,456,645 B2
Semiconductor structure with silicon-germanium compound and manufacturing method thereof
Guangsu Shao, Hefei (CN); Pan Yuan, Hefei (CN); and Minmin Wu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN)
Filed on May 20, 2022, as Appl. No. 17/664,242.
Application 17/664,242 is a continuation of application No. PCT/CN2022/077803, filed on Feb. 25, 2022.
Claims priority of application No. 202111006058.3 (CN), filed on Aug. 30, 2021.
Prior Publication US 2023/0066811 A1, Mar. 2, 2023
Int. Cl. H01L 21/762 (2006.01); H01L 21/304 (2006.01)
CPC H01L 21/76224 (2013.01) [H01L 21/3043 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor structure, comprising:
providing a substrate, the substrate comprising a first semiconductor material layer, a silicon-germanium compound layer and a second semiconductor material layer that are stacked sequentially;
forming, in the substrate, first trenches extending along a first direction and second trenches extending along a second direction, the first trenches and the second trenches separating the substrate into a plurality of spaced pillar structures, and the pillar structures each comprising the second semiconductor material layer, the silicon-germanium compound layer and a part of the first semiconductor material layer;
doping the pillar structures, such that one of the first semiconductor material layer and the second semiconductor material layer forms a source region and the other of the first semiconductor material layer and the second semiconductor material layer forms a drain region, and the silicon-germanium compound layer forms a channel region; and
forming a dielectric layer on an outer peripheral surface of each of the pillar structures, and a gate on an outer peripheral surface of the dielectric layer, the gate being opposite to at least a part of the channel region;
wherein the forming, in the substrate, first trenches extending along a first direction and second trenches extending along a second direction, the first trenches and the second trenches separating the substrate into a plurality of spaced pillar structures, and the pillar structures each comprising the second semiconductor material layer, the silicon-germanium compound layer and a part of the first semiconductor material layer comprises:
forming, in the substrate, the first trenches extending along the first direction, the first trenches penetrating through the second semiconductor material layer and the silicon-germanium compound layer, and extending to the first semiconductor material layer;
forming, in the first trenches, a first insulating layer and a sacrificial layer that are stacked; and
etching a part of the substrate and a part of the sacrificial layer to form the second trenches extending along the second direction, the second trenches exposing the first insulating layer;
wherein a top of the first insulating layer is lower than a top of the first semiconductor material layer.