US 12,456,630 B2
Method of manufacturing semiconductor structure having heat dissipation structure
Shing-Yih Shih, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Jul. 5, 2022, as Appl. No. 17/857,752.
Prior Publication US 2024/0014048 A1, Jan. 11, 2024
Int. Cl. H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01)
CPC H01L 21/4882 (2013.01) [H01L 23/3677 (2013.01); H01L 23/3733 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 23/3142 (2013.01); H01L 23/367 (2013.01); H01L 23/481 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/35121 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure, comprising:
forming a thermal conductive structure embedded within a first passivation layer of a first wafer, wherein the thermal conductive structure is disposed between an upper surface and a lower surface of the first passivation layer;
forming a plurality of conductive vias penetrating a first substrate of the first wafer and in contact with the thermal conductive structure through the lower surface of the first passivation layer;
forming a first connecting structure in contact with the thermal conductive structure and exposed by the upper surface of the first passivation layer;
bonding the first connecting structure of the first wafer to a second connecting structure of a second wafer; and
bonding the first passivation layer of the first wafer to a first dielectric layer of the second wafer, wherein the first passivation layer is disposed between the first substrate and the first dielectric layer of the second wafer
wherein a first seal ring embedded within the first dielectric layer of the second wafer is thermally connected to the thermal conductive structure through the first connecting structure and the second connecting structure, and
wherein the first dielectric layer of the second wafer comprises a first circuit region and a second dielectric layer of the third wafer comprises a second circuit region, and wherein the first circuit region and the second circuit region are located on opposite sides of the second substrate.