US 12,456,618 B2
Semiconductor-on-insulator (SOI) substrate and method for forming
Cheng-Ta Wu, Shueishang Township (TW); Chia-Ta Hsieh, Tainan (TW); Kuo Wei Wu, Tainan (TW); Yu-Chun Chang, Tainan (TW); and Ying Ling Tseng, Kaohsiung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 2, 2024, as Appl. No. 18/761,373.
Application 18/761,373 is a continuation of application No. 18/328,102, filed on Jun. 2, 2023, granted, now 12,062,539.
Application 18/328,102 is a continuation of application No. 17/701,103, filed on Mar. 22, 2022, granted, now 11,705,328, issued on Jul. 18, 2023.
Application 17/701,103 is a continuation of application No. 16/943,198, filed on Jul. 30, 2020, granted, now 11,289,330, issued on Mar. 29, 2022.
Claims priority of provisional application 62/907,976, filed on Sep. 30, 2019.
Prior Publication US 2024/0355618 A1, Oct. 24, 2024
Int. Cl. H01L 21/02 (2006.01); H01L 21/762 (2006.01); H10D 62/10 (2025.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01)
CPC H01L 21/02359 (2013.01) [H01L 21/76251 (2013.01); H10D 62/115 (2025.01); H10D 86/01 (2025.01); H10D 86/201 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a semiconductor base;
a dielectric layer disposed over the semiconductor base;
a semiconductor device layer overlying the dielectric layer,
wherein the dielectric layer comprises a first halogen concentration profile including a first minimum concentration within the dielectric layer, and wherein the semiconductor base has a second halogen concentration profile including a second minimum concentration within the semiconductor base, the second minimum concentration being less than the first minimum concentration; and
wherein the second halogen concentration profile comprises a uniformly doped region between a pair of interfacial regions.