US 12,456,602 B2
Semiconductor processing chambers and methods for deposition and etch
Khokan Chandra Paul, Cupertino, CA (US); Ravikumar Patil, Karnataka (IN); Vijet Patil, Bangalore (IN); Carlaton Wong, Sunnyvale, CA (US); Adam J. Fischbach, Campbell, CA (US); Timothy Franklin, Campbell, CA (US); Tsutomu Tanaka, Santa Clara, CA (US); and Canfeng Lai, Fremont, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Jun. 28, 2023, as Appl. No. 18/342,848.
Application 18/342,848 is a continuation of application No. 17/014,195, filed on Sep. 8, 2020, granted, now 11,699,571.
Prior Publication US 2023/0343552 A1, Oct. 26, 2023
Int. Cl. C23C 16/458 (2006.01); C23C 16/509 (2006.01); H01J 37/32 (2006.01); H01L 21/67 (2006.01); H01L 21/683 (2006.01)
CPC H01J 37/32091 (2013.01) [C23C 16/4586 (2013.01); C23C 16/509 (2013.01); H01J 37/32715 (2013.01); H01L 21/67069 (2013.01); H01L 21/6833 (2013.01); H01J 2237/2007 (2013.01); H01J 2237/20235 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A processing method, comprising:
forming a plasma of a silicon-containing precursor;
depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor, wherein the semiconductor substrate is housed in a processing region of a semiconductor processing chamber, wherein the semiconductor substrate defines a feature within the semiconductor substrate, and wherein the processing region is at least partially defined between a faceplate and a substrate support on which the semiconductor substrate is seated;
flowing a purge gas vertically through a purge path defined between a pedestal shaft and a platen insulator and downward between a rod insulator and a RF rod;
forming a treatment plasma within the processing region of the semiconductor processing chamber; and
densifying the flowable film within the feature defined within the semiconductor substrate with plasma effluents of the treatment plasma.