US 12,456,538 B2
Semiconductor storage device
Daishi Isogai, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 18/261,631
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Jan. 12, 2022, PCT No. PCT/JP2022/000708
§ 371(c)(1), (2) Date Jul. 14, 2023,
PCT Pub. No. WO2022/158349, PCT Pub. Date Jul. 28, 2022.
Claims priority of application No. 2021-008944 (JP), filed on Jan. 22, 2021.
Prior Publication US 2024/0395354 A1, Nov. 28, 2024
Int. Cl. G11C 29/56 (2006.01)
CPC G11C 29/56008 (2013.01) [G11C 29/56016 (2013.01); G11C 2029/5602 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor storage device, comprising:
a memory that includes a memory cell array, wherein
the memory cell array includes a plurality of memory cells, and
the memory is configured to read data from the memory cell array;
a read data output unit configured to output the read data with no change, wherein the read data has a bit width of m bits; and
a defect information obtaining unit configured to:
detect at least one of a plurality of defects in the read data;
obtain defect information indicating the at least one of the plurality of defects; and
output the defect information, wherein the defect information obtaining unit includes an adder that is configured to:
determine a number of defects of the plurality of defects in the read data; and
control the number of defects such that the number of defects is less than or equal to a threshold value, wherein
the number of defects in the read data is 0 to n bits,
n is less than m,
the defect information includes a respective value for each of the plurality of defects,
the respective value for each of the plurality of defects corresponds to 2 to n bit values, and
each of the 2 to n bit values indicates 1-bit information for the each of the plurality of defects.