| CPC G11C 29/022 (2013.01) [G11C 29/76 (2013.01); G11C 29/789 (2013.01)] | 20 Claims | 

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               1. A storage device, comprising: 
            a volatile memory including a memory cell array, which has a plurality of sub-cell arrays therein, and a plurality of sub-wordline driver blocks, which are configured to drive sub-wordlines electrically connected to at least one of the plurality of sub-cell arrays; and 
                a storage controller configured to control the volatile memory, said storage controller comprising: 
              a volatile memory interface configured to transmit data to and receive data from the volatile memory, and detect an error bit(s) of data output from the volatile memory; 
                  a working memory configured to store a structure map table, which maps unit areas of the volatile memory, the sub-wordlines, and the plurality of sub-wordline driver blocks; and 
                  a processor configured to: update an error count of a unit area of the volatile memory that corresponds to the error bit(s) detected from the volatile memory interface to the structure map table, detect at least one of a defective sub-wordline and defective sub-wordline driver block, by accessing the structure map table, and then repair at least one memory cell connected to the defective sub-wordline and/or repair at least one memory cell associated with the defective sub-wordline driver block, in response to the detection of the at least one of a defective sub-wordline and defective sub-wordline driver block. 
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