US 12,456,533 B2
Shift register and driving method therefor, and display substrate and display apparatus
Zhichong Wang, Beijing (CN); Peng Liu, Beijing (CN); and Jing Feng, Beijing (CN)
Assigned to Beijing BOE Technology Development Co., Ltd., Beijing (CN)
Appl. No. 18/689,081
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Aug. 23, 2022, PCT No. PCT/CN2022/114317
§ 371(c)(1), (2) Date Mar. 5, 2024,
PCT Pub. No. WO2024/040442, PCT Pub. Date Feb. 29, 2024.
Prior Publication US 2025/0131968 A1, Apr. 24, 2025
Int. Cl. G11C 19/28 (2006.01); G09G 3/3233 (2016.01); H10K 59/131 (2023.01); H01L 21/77 (2017.01); H10K 59/12 (2023.01); H10K 71/20 (2023.01)
CPC G11C 19/287 (2013.01) [G09G 3/3233 (2013.01); H10K 59/131 (2023.02); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); H01L 21/77 (2013.01); H10K 59/1201 (2023.02); H10K 71/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A shift register, comprising a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a first output sub-circuit, and a second output sub-circuit;
the first control sub-circuit is respectively connected with a signal input terminal, a first node, a second node, a first clock signal terminal, a second clock signal terminal, and a first power supply terminal, and is configured to provide a signal of the signal input terminal to the first node under control of signals from the first clock signal terminal, the second clock signal terminal, the second node, and the first power supply terminal and maintain a potential of the first node;
the second control sub-circuit is respectively connected with a second power supply terminal, the first clock signal terminal, the first node, and the second node, and is configured to provide a signal of the second power supply terminal or the first clock signal terminal to the second node under control of signals from the first clock signal terminal and the first node;
the third control sub-circuit is respectively connected with the first node, the second node, a fourth node, the second clock signal terminal, and the first power supply terminal, and is configured to provide a signal of the second clock signal terminal or the first power supply terminal to the fourth node under control of signals from the second clock signal terminal, the first node, and the second node and maintain a potential of the fourth node;
the first output sub-circuit is respectively connected with the first power supply terminal, the second power supply terminal, the first node, the fourth node, and a first signal output terminal, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the first signal output terminal under control of signals from the first node and the fourth node; and
the second output sub-circuit is connected with the first signal output terminal, the third control sub-circuit, the first power supply terminal, the second power supply terminal, and a second signal output terminal, respectively, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the second signal output terminal under control of signals from the third control sub-circuit and the first signal output terminal.