| CPC G11C 17/18 (2013.01) [G11C 7/1045 (2013.01); G11C 7/222 (2013.01)] | 15 Claims |
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1. An eFuse one-time programmable (OTP) memory, comprising:
an eFuse intellectual property (IP) configured to perform one-time writing and readings for a plurality of memory cells; and
a serial interface (SI) logic configured to receive a clock signal and a trim signal from a master device, generate a main clock signal based on the clock signal, recognize the trim signal based on the main clock signal, and perform data writing to, or reading from, the eFuse IP based on the clock signal and the trim signal,
wherein the trim signal comprises a start signal, a mode signal configured for a write mode or a read mode, and control signals configured to read or write for each of a plurality of addresses corresponding to the plurality of memory cells,
wherein in the read mode, the serial interface logic is configured to determine whether to read from an n-th address based on a control signal for the n-th address among the control signals, and in response to the read from the n-th address being determined, output a signal for the n-th address to the eFuse IP, and
wherein the signal for the n-th address has an n-th bit being 1 and other bits being 0.
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