US 12,456,530 B2
Semiconductor device for programming or erasing select transistors and method of operating the same
Hyung Jin Choi, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on May 1, 2023, as Appl. No. 18/310,290.
Claims priority of application No. 10-2022-0159852 (KR), filed on Nov. 25, 2022.
Prior Publication US 2024/0177783 A1, May 30, 2024
Int. Cl. G11C 16/14 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/12 (2006.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/12 (2013.01); G11C 16/14 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01); G11C 16/3445 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating a semiconductor device, comprising:
applying a program voltage to select lines, which are coupled to corresponding select transistors that is included in at least one string group of a plurality of string groups; and
performing a verify operation on the select transistors,
wherein performing the verify operation comprises:
performing a verify check operation on first select transistors that is included in a first string group, of the plurality of string groups; and applying a verify voltage to a select line coupled to second select transistors that is included in a second string group of the plurality of string groups,
wherein the performing the verify check operation on the first select transistors and the applying the verify voltage to a select line coupled to the second select transistors are performed simultaneously.