US 12,456,528 B2
Dual-way sensing scheme for better neighboring word-line interference
Dengtao Zhao, Los Gatos, CA (US); Deepanshu Dutta, Fremont, CA (US); Peng Zhang, San Jose, CA (US); and Heguang Li, Newark, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Sandisk Technologies, Inc., Milpitas, CA (US)
Filed on Sep. 7, 2022, as Appl. No. 17/939,748.
Prior Publication US 2024/0079068 A1, Mar. 7, 2024
Int. Cl. G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3427 (2013.01) [G11C 16/10 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A storage device, comprising:
a non-volatile memory, the non-volatile memory including a block of N wordlines partitioned into a plurality of sub-blocks, the plurality of sub-blocks including an upper sub-block of a first subset of the block of N wordlines and located on a drain side of the block and including a lower sub-block of a second subset of the block of N wordlines and located on a source side of the block; and
control circuitry coupled to the block of N wordlines and configured to:
perform a program operation in a normal order programming sequence on the first upper sub-block;
perform a sensing operation on the upper sub-block using a reverse sensing scheme, the reverse sensing scheme including charging a first sense capacitor with current conducted through a first NAND string and a first bit line then analyzing a potential of the first sense capacitor after charging is completed;
perform a program operation in a reverse order programming sequence on the lower sub-block; and
perform a sensing operation on the lower sub-block using a regular sensing scheme, the regular sensing scheme including discharging the first sense capacitor through the first bit line and then through the first NAND string and then analyzing a potential of the first sense capacitor after discharging is completed.