US 12,456,527 B2
Reconfigurable lines in different sub-block modes in a NAND memory device
Wei Cao, Fremont, CA (US); and Xiang Yang, Santa Clara, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Sandisk Technologies, Inc., Milpitas, CA (US)
Filed on Jul. 31, 2023, as Appl. No. 18/228,156.
Claims priority of provisional application 63/467,084, filed on May 17, 2023.
Prior Publication US 2024/0386971 A1, Nov. 21, 2024
Int. Cl. G11C 16/28 (2006.01); G11C 16/08 (2006.01)
CPC G11C 16/28 (2013.01) [G11C 16/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of programming a memory device, comprising the steps of:
providing a memory block that includes a plurality of memory cells arranged in a plurality of word lines, the plurality of word lines including at least two reconfigurable word lines that are dummy word lines when the memory block is operating in a one bit per memory cell mode and that are data word lines when the memory block is operating in a multiple bits per memory cell mode;
determining if a selected word line of the plurality of word lines is one of the at least two reconfigurable word lines;
in response to the selected word line not being one of the at least two reconfigurable word lines, programming the memory cells of the selected word line with a first programming scheme; and
in response to the selected word line being one of the at least two reconfigurable word lines, programming the memory cells of the selected word line with a second programming scheme that is different than the first programming scheme.