| CPC G11C 16/26 (2013.01) [G11C 16/24 (2013.01)] | 19 Claims |
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1. A memory device comprising:
a memory cell array including a plurality of memory cells;
a peripheral circuit including a plurality of page buffers respectively connected to the plurality of memory cells through a plurality of bit lines;
a sensing circuit connected to the plurality of page buffers respectively through a plurality of sensing lines, the sensing circuit:
performing a sensing operation on the page buffers in units of a plurality of chunks, each chunk including two or more page buffers, among the plurality of page buffers, and
outputting a sensing result of each of the plurality of chunks;
a verification result output circuit configured to output a final verification result of a target program state, among a plurality of program states to which the memory cells are to be programmed, based on the sensing results of the plurality of chunks; and
a control logic configured to control the sensing circuit and the peripheral circuit based on the final verification result,
wherein the verification result output circuit is configured to output a final verification result representing that a verification on the target program state has passed when a sensing result of at least one chunk group, among a plurality of chunk groups, formed by classifying the plurality of chunks, represents pass.
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