US 12,456,522 B2
Memory device and methods of erasure operation using different float times for string selection transistors
SongMin Jiang, Hubei (CN); HongTao Liu, Hubei (CN); Ying Huang, Hubei (CN); and Lei Guan, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Sep. 26, 2023, as Appl. No. 18/475,027.
Claims priority of application No. 202310793195.9 (CN), filed on Jun. 29, 2023.
Prior Publication US 2025/0006274 A1, Jan. 2, 2025
Int. Cl. G11C 16/16 (2006.01); G11C 5/02 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 19/28 (2006.01); H10B 41/43 (2023.01); H10B 41/44 (2023.01); H10B 41/49 (2023.01)
CPC G11C 16/16 (2013.01) [G11C 5/025 (2013.01); G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 19/285 (2013.01); H10B 41/43 (2023.02); H10B 41/44 (2023.02); H10B 41/49 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory, comprising:
a memory array, the memory array comprising a block and a first selection line, the block comprising a plurality of strings, each string comprising a first selection transistor, the first selection line being coupled to the first selection transistor; and
a peripheral circuit, the peripheral circuit being coupled to the first selection line, and being configured to perform an erase operation on the plurality of strings in the block; wherein to perform the erase operation, the peripheral circuit is configured to:
at a first moment, float a first selection line coupled to a first selection transistor of a first string, the first string being a string that has been erased among the plurality of strings; and
at a second moment after the first moment, float a first selection line coupled to a first selection transistor of a second string, the second string being a string that has not been erased among the plurality of strings.