US 12,456,521 B2
Sub-block separation in NAND memory through word line based selectors
Motoo Ohaga, Nagoya (JP); Shinsuke Yada, Nagoya (JP); Naohiro Hosoda, Asachi-cho (JP); and Hiroyuki Ogawa, Nagoya (JP)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Sandisk Technologies, Inc., Milpitas, CA (US)
Filed on Nov. 1, 2023, as Appl. No. 18/499,797.
Prior Publication US 2025/0140318 A1, May 1, 2025
Int. Cl. G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-volatile memory device, comprising:
an array of non-volatile memory cells comprising a plurality of blocks, each of the blocks having a NAND architecture and comprising:
a source line;
a plurality of bit lines;
a plurality of NAND strings each comprising a plurality of memory cells connected in series between the source line and a corresponding bit line; and
a plurality of word lines along each of which is connected a corresponding memory cell of each of the NAND strings, the word lines including:
a plurality of data word lines; and
a plurality of select word lines positioned on the NAND strings between the data word lines and either the bit lines or the source line, each of the plurality of select word lines programmed to one of a distinct sets of threshold value combinations to select one of N distinct subsets of the NAND strings in response to a corresponding one of a set of N distinct bias voltage combinations, where N is an integer greater than or equal to two.