US 12,456,520 B2
Non-volatile memory device, storage device having the same and operating method of non-volatile memory device
Jayang Yoon, Suwon-si (KR); Chihyun Kim, Suwon-si (KR); Sangsoo Park, Suwon-si (KR); Junehong Park, Suwon-si (KR); Chiweon Yoon, Suwon-si (KR); and Hyeongdo Choi, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 20, 2023, as Appl. No. 18/382,325.
Claims priority of application No. 10-2023-0004928 (KR), filed on Jan. 12, 2023.
Prior Publication US 2024/0242765 A1, Jul. 18, 2024
Int. Cl. G11C 11/34 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/08 (2013.01); G11C 16/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-volatile memory device comprising:
a memory cell array including memory cells coupled to a plurality of word lines;
a boost circuit configured to receive an external power supply voltage and generate a boosted voltage based on the external power supply voltage;
a regulator configured to generate a regulated voltage based on the external power supply voltage; and
a control logic configured to control word line voltages provided to the plurality of word lines,
wherein the control logic performs a plurality of program loops in a program operation for the memory cell array, and
wherein the control logic provides an adjacent word line voltage to at least one adjacent word line that is adjacent to a selected word line, and
wherein, in a first section of the plurality of program loops, the control logic provides the regulated voltage as the adjacent word line voltage, and in a second section of the plurality of program loops, the control logic provides the boosted voltage as the adjacent word line voltage.