US 12,456,518 B2
Nonvolatile semiconductor memory including a read operation
Makoto Iwai, Yokohama Kanagawa (JP); and Hiroshi Nakamura, Fujisawa Kanagawa (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Mar. 6, 2024, as Appl. No. 18/596,753.
Application 14/023,607 is a division of application No. 13/899,843, filed on May 22, 2013, granted, now 8,559,222, issued on Oct. 15, 2013.
Application 18/596,753 is a continuation of application No. 17/371,568, filed on Jul. 9, 2021, granted, now 11,948,640.
Application 17/371,568 is a continuation of application No. 16/844,258, filed on Apr. 9, 2020, granted, now 11,087,845, issued on Aug. 10, 2021.
Application 16/844,258 is a continuation of application No. 16/149,862, filed on Oct. 2, 2018, granted, now 10,658,039, issued on May 19, 2020.
Application 16/149,862 is a continuation of application No. 15/337,592, filed on Oct. 28, 2016, granted, now 10,109,359, issued on Oct. 23, 2018.
Application 15/337,592 is a continuation of application No. 14/886,193, filed on Oct. 19, 2015, granted, now 9,514,836, issued on Dec. 6, 2016.
Application 14/886,193 is a continuation of application No. 14/263,948, filed on Apr. 28, 2014, granted, now 9,384,848, issued on Jul. 5, 2016.
Application 14/263,948 is a continuation of application No. 14/023,607, filed on Sep. 11, 2013, granted, now 8,750,039, issued on Jun. 10, 2014.
Application 13/899,843 is a continuation of application No. 13/490,541, filed on Jun. 7, 2012, granted, now 8,477,534, issued on Jul. 2, 2013.
Application 13/490,541 is a continuation of application No. 13/193,968, filed on Jul. 29, 2011, granted, now 8,223,543, issued on Jul. 17, 2012.
Application 13/193,968 is a continuation of application No. 12/563,296, filed on Sep. 21, 2009, granted, now 8,009,470, issued on Aug. 30, 2011.
Claims priority of application No. 2008-308608 (JP), filed on Dec. 3, 2008.
Prior Publication US 2024/0212757 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/34 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/06 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/0483 (2013.01) [G11C 11/56 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 11/5642 (2013.01); G11C 16/06 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/3436 (2013.01); G11C 16/3454 (2013.01); G11C 16/3459 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first transistor;
a second transistor;
a plurality of memory cells electrically connected in series between the first transistor and the second transistor;
a source line electrically connected to the first transistor;
a bit line electrically connected to the second transistor;
a plurality of word lines electrically connected to gates of the plurality of memory cells, respectively;
a sense amplifier including:
a first node,
a third transistor including i) a first end electrically connected to the bit line and ii) a second end electrically connected to the first node,
a fourth transistor including a first end electrically connected i) to the second end of the third transistor and ii) to the first node,
a fifth transistor including a gate electrically connected to the first node,
a sixth transistor including one end electrically connected to a first end of the fifth transistor,
a first latch electrically connected to a second end of the fifth transistor, and
a second latch electrically connected to the second end of the fifth transistor; and
a controller configured to perform an operation including:
a first period,
a second period after the first period,
a third period after the second period,
a fourth period after the third period, and
a fifth period after the fourth period,
at least during the second to fifth periods, a first voltage being applied to one of the plurality of word lines, and a second voltage higher than the first voltage being applied to another one of the plurality of word lines,
during the first period, a third voltage being applied to a gate of the fourth transistor to turn on the fourth transistor,
during the second period, a fourth voltage being applied to the gate of the fourth transistor to turn off the fourth transistor, and a fifth voltage being applied to a gate of the third transistor to turn on the third transistor,
during the third period, a sixth voltage being applied to a gate of the sixth transistor to turn on the sixth transistor,
during the fourth period, a seventh voltage being applied to the gate of the third transistor to turn on the third transistor, and
during the fifth period, an eighth voltage being applied to the gate of the sixth transistor to turn on the sixth transistor.