US 12,456,517 B2
Semiconductor flash memory device with voltage control on completion of a program operation and subsequent to completion of the program operation
Kenrou Kikuchi, Yokohama (JP); and Yasuhiro Shimura, Yokohama (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Feb. 29, 2024, as Appl. No. 18/591,563.
Application 18/591,563 is a continuation of application No. 18/106,520, filed on Feb. 7, 2023, granted, now 11,948,642.
Application 18/106,520 is a continuation of application No. 17/004,272, filed on Aug. 27, 2020, granted, now 11,600,327, issued on Mar. 7, 2023.
Claims priority of application No. 2019-163385 (JP), filed on Sep. 6, 2019.
Prior Publication US 2024/0203498 A1, Jun. 20, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/0483 (2013.01) [G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method of controlling a semiconductor memory device,
the semiconductor memory device comprising:
a first memory string including a plurality of first memory cell transistors connected to each other in series;
a plurality of word lines connected to the plurality of first memory cell transistors, respectively;
a first select transistor connected to one end of the first memory string;
a first gate line connected to the first select transistor;
a second select transistor connected to another end of the first memory string;
a second gate line connected to the second select transistor;
a bit line connected to the first select transistor;
a source line connected to the second select transistor; and
a control circuit configured to execute a program operation, the program operation including a plurality of write operations and a plurality of verify operations, the plurality of write operations writing data to the plurality of first memory cell transistors, wherein
among the plurality of first memory cell transistors, a memory cell transistor to which data is to be written is a first write target transistor,
among the plurality of word lines, a word line connected to the first write target transistor is a select word line,
among the plurality of word lines, a word line closer to the bit line than the select word line is a first non-select word line, and
among the plurality of word lines, a word line closer to the source line than the select word line is a second non-select word line,
when the control circuit receives a signal of starting a read operation during the program operation,
the method comprising:
applying, to the select word line, a first voltage higher than a ground voltage;
applying, to the first non-select word line and the second non-select word line, a second voltage higher than the ground voltage;
completing the program operation;
applying, to the select word line, a third voltage higher than the ground voltage; and
applying, to the first non-select word line and the second non-select word line, a fourth voltage higher than the ground voltage, wherein
the voltages applied to the select word line, the first non-select word line, and the second non-select word line are higher than or equal to the ground voltage in a period from when the control circuit receives the signal of starting the read operation to when the read operation starts, and wherein
after the third voltage applied to the select word line, the fourth voltage applied to the first non-select word line and the second non-select word line, the read operation starts.