US 12,456,514 B2
Buried metal techniques
Rahul Mathur, Austin, TX (US); and Mudit Bhargava, Austin, TX (US)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Jul. 27, 2022, as Appl. No. 17/874,611.
Prior Publication US 2024/0038297 A1, Feb. 1, 2024
Int. Cl. G11C 11/419 (2006.01); G11C 11/412 (2006.01); H10B 10/00 (2023.01)
CPC G11C 11/419 (2013.01) [G11C 11/412 (2013.01); H10B 10/12 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A device comprising:
bitline drivers coupled to passgates of bitcells via bitlines; and
buried metal lines formed within a substrate including a buried enable signal line and a buried ground line coupled to ground connections of the bitline drivers,
wherein the buried enable signal line transfers a negative bias to a selected bitline of the bitlines via the buried ground line that is coupled to the ground connections of the bitline drivers so as to increase gate-source bias of the passgates of a selected bitcell to thereby enhance write capability of the selected bitcell.