US 12,456,511 B2
Memory circuit and method of operating same
Sanjeev Kumar Jain, Hsinchu (TW); Ishan Khera, Hsinchu (TW); and Atul Katoch, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Mar. 11, 2024, as Appl. No. 18/601,367.
Application 18/601,367 is a continuation of application No. 17/746,124, filed on May 17, 2022, granted, now 11,929,110.
Claims priority of provisional application 63/283,408, filed on Nov. 26, 2021.
Prior Publication US 2024/0221820 A1, Jul. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 11/4093 (2006.01); H03K 19/20 (2006.01)
CPC G11C 11/4087 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4085 (2013.01); G11C 11/4093 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory circuit comprising:
a global control circuit configured to generate a first set of global pre-decoder signals, a second set of global pre-decoder signals and a first set of local address signals in response to a memory address signal and a first clock signal;
a first local control circuit coupled to the global control circuit, the first local control circuit comprising:
a first set of repeater circuits configured to generate a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and to generate a second set of local pre-decoder signals in response to the second set of global pre-decoder signals; and
a first clock pre-decoder circuit coupled to the global control circuit, and configured to generate a first set of clock signals and a second set of clock signals in response to the first set of local address signals and the first clock signal; and
a first set of word line post-decoder circuits coupled to the first clock pre-decoder circuit and the first set of repeater circuits, and configured to generate a first set of word line signals in response to the first set of clock signals, the first set of local pre-decoder signals and the second set of local pre-decoder signals.