| CPC G11C 11/4078 (2013.01) [G11C 11/4087 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01)] | 20 Claims |
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1. A semiconductor memory device comprising:
a memory cell array comprising a plurality of memory cell rows, wherein each memory cell row of the plurality of memory cell rows comprises a plurality of memory cells;
a row hammer management circuit configured to:
count a number of accesses to the each memory cell row based on an active command received from an external memory controller and store the counted number in at least one count cell in the each memory cell row as count data, and
based on a first command received after the active command, perform an internal read-update-write operation to read the count data from the at least one count cell in a target memory cell row from among the plurality of memory cell rows, to update the read count data, and to write the updated count data in the at least one count cell in the target memory cell row; and
a column decoder configured to:
access a first memory cell from among a first plurality of memory cells included in a first memory cell row from among the plurality of memory cell rows using a first bit-line, based on a column address; and
store data in the first memory cell using a first power supply voltage, or perform an internal write operation to store the count data in the first memory cell using a second power supply voltage during an internal write time interval smaller than a reference write time interval,
wherein a voltage level of the second power supply voltage is greater than a voltage level of the first power supply voltage.
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