US 12,456,508 B2
Memory device, operation method of a memory device, and operation method of a memory controller
Taeyoung Oh, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 14, 2023, as Appl. No. 18/169,151.
Claims priority of application No. 10-2022-0036244 (KR), filed on Mar. 23, 2022; and application No. 10-2022-0063064 (KR), filed on May 23, 2022.
Prior Publication US 2023/0305706 A1, Sep. 28, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 11/4076 (2006.01)
CPC G11C 11/4076 (2013.01) 20 Claims
OG exemplary drawing
 
19. A memory device, comprising:
a memory core;
a command/address decoder configured to receive a clock signal from a memory controller and to decode a command/address signal received from the memory controller based on the clock signal;
a data clock splitter configured to receive a data clock signal of a full rate from the memory controller and to generate four split data clocks by splitting the data clock signal;
a reception circuit configured to sequentially output write data received through a plurality of data signals from the memory controller to the memory core in synchronization with the four split data clocks; and
a transmission circuit configured to send read data received from the memory core to the memory controller through the plurality of data signals in synchronization with the four split data clocks; and
wherein, while the data clock signal of the full rate is being received from the memory controller, the data clock splitter is further configured to perform a synchronization operation on the data clock signal based on a synchronization pattern received through at least one of the plurality of data signals.