US 12,456,505 B2
Staggering refresh address counters of a number of memory devices, and related methods, devices, and systems
Christopher G. Wieduwilt, Boise, ID (US); and James S. Rehmeyer, Boise, ID (US)
Assigned to Lodestar Licensing Group LLC, Evanston, IL (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Jan. 26, 2024, as Appl. No. 18/424,669.
Application 18/424,669 is a continuation of application No. 17/387,428, filed on Jul. 28, 2021, granted, now 11,887,649.
Application 17/387,428 is a continuation of application No. 16/987,168, filed on Aug. 6, 2020, granted, now 11,120,860, issued on Sep. 14, 2021.
Prior Publication US 2024/0161805 A1, May 16, 2024
Int. Cl. G11C 11/40 (2006.01); G11C 11/406 (2006.01)
CPC G11C 11/406 (2013.01) [G11C 11/40603 (2013.01); G11C 11/40618 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a host device; and
a first memory device and a second memory device, each configured to be refreshed responsive to a receipt of a refresh command from the host device substantially simultaneously, wherein a count value of a refresh address counter of the first memory device is different than a count value of a refresh address counter of the second memory device such that an address of a row of the first memory device that is refreshed is different than an address of a row of the second memory device that is refreshed, wherein a difference between the count value of the refresh address counter of the first memory device and the count value of the refresh address counter of the second memory device is at least partially based on a refresh rate of at least one of the first memory device or the second memory device.