| CPC G11C 7/1069 (2013.01) [G11C 7/1057 (2013.01); G11C 7/106 (2013.01)] | 20 Claims |
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1. A memory device comprising:
a memory array comprising a plurality of memory cells, the plurality of memory cells comprising a set of target cells connected to a target wordline, wherein for each target cell of the set of target cells, a respective group of adjacent cells adjacent to the target cell comprises at least one cell connected to at least one wordline adjacent to the target wordline; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a read operation to be initiated with respect to the set of target cells;
obtaining, for the respective group of adjacent cells, respective cell state information;
performing a set of strobe reads on the set of target cells;
identifying, by performing a lookup of a reference table, a first strobe read and a second strobe read, from the set of strobe reads, for generating semi-soft bit data based on the respective cell state information of the respective group of adjacent cells; and
generating, for a target cell of the set of target cells, the semi-soft bit data based on data obtained from the first strobe read and the second strobe read.
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