US 12,456,501 B2
Address decoding method, and memory controller and semiconductor memory system using the same
Chinam Kim, Suwon-si (KR); Tae-Kyeong Ko, Suwon-si (KR); and Cholmin Kim, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 13, 2023, as Appl. No. 18/209,057.
Claims priority of application No. 10-2022-0164892 (KR), filed on Nov. 30, 2022.
Prior Publication US 2024/0177746 A1, May 30, 2024
Int. Cl. G11C 7/10 (2006.01)
CPC G11C 7/1039 (2013.01) [G11C 7/1069 (2013.01); G11C 7/1096 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor memory system comprising:
a memory device comprising a plurality of banks; and
a memory controller configured to generate an offset address for a first bank among the plurality of banks and a command indicating the offset address, based on a first request, and transmit the offset address and the command to the memory device,
wherein the memory device is configured to receive the offset address and the command, generate a first address by adding the offset address to a base address for the first bank, according to the command, and perform a memory operation on the first address of the first bank according to the command.