US 12,456,499 B2
Three-dimensional memory device including laterally separated source lines and method of making the same
Masaaki Higashitani, Cupertino, CA (US); James Kai, Santa Clara, CA (US); and Johann Alsmeier, San Jose, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Jul. 11, 2023, as Appl. No. 18/350,573.
Claims priority of provisional application 63/379,805, filed on Oct. 17, 2022.
Prior Publication US 2024/0127864 A1, Apr. 18, 2024
Int. Cl. G11C 5/06 (2006.01); G11C 16/04 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC G11C 5/063 (2013.01) [G11C 16/0483 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first memory block comprising first word lines and a first source layer segment; and
a second memory block comprising second word lines and a second source layer segment which is electrically isolated from the first source layer segment,
wherein the first word lines in the first memory block are electrically connected to the respective second word lines in the second memory block across a first word line bridge region located between the first memory block and the second memory block.