US 12,456,437 B2
Display device with drive circuit
Tadayoshi Katsuta, Tokyo (JP)
Assigned to Magnolia White Corporation, Tokyo (JP)
Filed by Magnolia White Corporation, Tokyo (JP)
Filed on Aug. 21, 2023, as Appl. No. 18/235,994.
Claims priority of application No. 2022-131885 (JP), filed on Aug. 22, 2022.
Prior Publication US 2024/0062734 A1, Feb. 22, 2024
Int. Cl. G09G 3/36 (2006.01)
CPC G09G 3/3677 (2013.01) [G09G 2310/061 (2013.01); G09G 2320/0247 (2013.01); G09G 2320/046 (2013.01); G09G 2330/022 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A display device comprising:
a pixel comprising a pixel transistor and a pixel electrode coupled to a first electrode of the pixel transistor;
a scanning line coupled to a gate of the pixel transistor;
a signal line coupled to a second electrode of the pixel transistor; and
a drive circuit configured to be supplied with a first power supply voltage signal of a positive value and a second power supply voltage signal of a negative value to drive the pixel transistor,
wherein the drive circuit comprises:
a gate driver configured to supply a scanning signal to the scanning line;
a signal line selection circuit configured to supply a pixel signal to the signal line; and
a display control circuit configured to control the gate driver and the signal line selection circuit,
wherein holding capacitance is provided between the pixel electrode and a common electrode supplied with a common potential lower than a GND potential in a display operation, and
wherein the drive circuit comprises:
a first switch circuit configured to be turned on at first time in a power-off sequence to supply the first power supply voltage signal to the scanning line;
a second switch circuit configured to be turned on at the first time to supply the GND potential to the signal line; and
a reset circuit configured to maintain an ON state of the first switch circuit and the second switch circuit after control on the gate driver and the signal line selection circuit is stopped at second time after the first time at which the first switch circuit and the second switch circuit are turned on.