US 12,456,436 B2
Staged gate voltage control
Karl Raymond Amundson, Cambridge, MA (US); and Yuval Ben-Dov, Cambridge, MA (US)
Assigned to E Ink Corporation, Billerica, MA (US)
Filed by E INK CORPORATION, Billerica, MA (US)
Filed on Sep. 30, 2024, as Appl. No. 18/901,550.
Claims priority of provisional application 63/588,290, filed on Oct. 5, 2023.
Prior Publication US 2025/0118271 A1, Apr. 10, 2025
Int. Cl. G09G 3/34 (2006.01); G02F 1/167 (2019.01); G02F 1/16766 (2019.01); G02F 1/1685 (2019.01)
CPC G09G 3/344 (2013.01) [G02F 1/167 (2013.01); G02F 1/16766 (2019.01); G02F 1/1685 (2019.01); G09G 2300/08 (2013.01); G09G 2310/06 (2013.01); G09G 2310/068 (2013.01); G09G 2320/0209 (2013.01); G09G 2320/0219 (2013.01)] 20 Claims
OG exemplary drawing
 
11. An electro-optic display comprising:
a light-transmissive common electrode;
a backplane including an array of pixel electrodes;
a layer of electro-optic material disposed between the common electrode and the array of pixel electrodes, wherein each pixel electrode is coupled to a pixel transistor including a source electrode, a gate electrode, and a drain electrode, and wherein the gate electrode is coupled to a gate line, the source electrode is coupled to a source line, and the drain electrode is coupled to the pixel electrode; and
a controller capable of applying time-dependent voltages to the gate line, the source line, and the common electrode, the controller configured to:
apply a first stage voltage to the gate line, wherein the first stage voltage has a first magnitude that is substantially half of a gate low voltage for placing the pixel transistor in a non-conducting state;
maintain the first stage voltage on the gate line for a first period of time; and
apply a second stage voltage to the gate line, wherein the second stage voltage has a second magnitude that is substantially the gate low voltage for placing the pixel transistor in the non-conducting state.