| CPC G09G 3/3266 (2013.01) [G09G 3/3291 (2013.01); G09G 2310/0278 (2013.01); G09G 2310/08 (2013.01)] | 20 Claims |
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1. A gate driving circuit, comprising:
first and second dummy stage circuits that are each capable of supplying a carry signal and each comprise a Q node, a QH node, and a QB node; and
a plurality of stage circuits that are each capable of supplying gate signals to a gate line and each include a Q node, a QH node, and a QB node,
wherein each of the plurality of stage circuits is connected to supply a respective gate signal to a corresponding gate line among a plurality of gate lines based on at least one of a plurality of carry signals from the first and second dummy stage circuits, one or more preceding stage circuits among the plurality of stage circuits, and one or more following stage circuits among the plurality of stage circuits, and
wherein when variable refresh rate driving is performed, the first and second dummy stage circuits are configured to operate such that:
a start signal is input to only the first dummy stage circuit among the first and second dummy stage circuits for enabling the first dummy stage circuit to be activated; and
a carry signal from the first dummy stage circuit is input to the second dummy stage circuits for enabling the second dummy stage circuit to be activated without the start signal.
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