| CPC G09G 3/3266 (2013.01) [G09G 2300/0426 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01)] | 20 Claims |
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1. A display device comprising:
a display panel including pixels; and
a gate driver configured to apply scan gate signals and sensing gate signals to the pixels,
wherein the gate driver includes an N-th stage (where N is a natural number) configured to output an N-th scan gate signal among the scan gate signals based on a scan clock signal, a voltage of a first node, and a voltage of a second node, and output an N-th sensing gate signal among the sensing gate signals based on a sensing clock signal, the voltage of the first node, and the voltage of the second node,
wherein the N-th stage includes a compensator, a sixth transistor including a control electrode connected to the first node, and a ninth transistor including a control electrode connected to the first node, and,
wherein, in a variable frequency mode, the compensator outputs a second signal to the first node in response to a first signal, and the sixth transistor does not output the N-th scan gate signal when the ninth transistor outputs the N-th sensing gate signal based on the sensing clock signal, the voltage of the first node, and the voltage of the second node.
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