US 12,456,427 B2
Array substrate and display apparatus
Changchang Liu, Beijing (CN); Yipeng Chen, Beijing (CN); and Mingkun Yang, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and Beijing BOE Technology Development Co., Ltd., Beijing (CN)
Appl. No. 18/694,497
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed May 9, 2023, PCT No. PCT/CN2023/092971
§ 371(c)(1), (2) Date Mar. 22, 2024,
PCT Pub. No. WO2024/229689, PCT Pub. Date Nov. 14, 2024.
Prior Publication US 2025/0246137 A1, Jul. 31, 2025
Int. Cl. G09G 3/3233 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An array substrate, comprising a plurality of pixel driving circuits and a plurality of gate lines;
wherein a respective pixel driving circuit of the plurality of pixel driving circuits comprises a driving transistor, a data write transistor, a first reset transistor, a first capacitor having a first capacitor electrode and a second capacitor electrode, a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and a first node connecting line;
a respective gate line of the plurality of gate lines is configured to provide gate scanning signal to the data write transistor in the respective pixel driving circuit;
a gate electrode of the driving transistor is connected to the third capacitor electrode;
the first node connecting line connects a second electrode of the first reset transistor with the third capacitor electrode; and
an orthographic projection of the respective gate line on a base substrate is substantially non-overlapping with an orthographic projection of the first node connecting line on the base substrate.