US 12,456,416 B2
Pixel driving circuit, display panel and driving method of pixel driving circuit
Ying-Hsiang Tseng, Shanghai (CN)
Assigned to Everdisplay Optronics (Shanghai) Co., Ltd., Shanghai (CN)
Appl. No. 18/681,528
Filed by Everdisplay Optronics (Shanghai) Co., Ltd., Shanghai (CN)
PCT Filed Feb. 23, 2023, PCT No. PCT/CN2023/077901
§ 371(c)(1), (2) Date Feb. 6, 2024,
PCT Pub. No. WO2024/124692, PCT Pub. Date Jun. 20, 2024.
Claims priority of application No. 202211606282.0 (CN), filed on Dec. 12, 2022.
Prior Publication US 2025/0131869 A1, Apr. 24, 2025
Int. Cl. G09G 3/32 (2016.01)
CPC G09G 3/32 (2013.01) [G09G 2320/0257 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A pixel driving circuit, comprising a plurality of pixel driving units, wherein the pixel driving unit comprises:
a first transistor, a first electrode of the first transistor being coupled to a fifth input terminal, a second electrode of the first transistor being coupled to a first node, and a gate electrode of the first transistor being coupled to a second input terminal;
a second transistor, a first electrode of the second transistor being coupled to a second node, a second electrode of the second transistor being coupled to a first power supply voltage, and a gate electrode of the second transistor being coupled to a first input terminal;
a third transistor, a first electrode of the third transistor being coupled to the second node, a second electrode of the third transistor being coupled to a third node, and a gate electrode of the third transistor being coupled to the second input terminal;
a fourth transistor, a first electrode of the fourth transistor being coupled to the first power supply voltage, a second electrode of the fourth transistor being coupled to a fourth node, and a gate electrode of the fourth transistor being coupled to a sixth input terminal;
a sixth transistor, a first electrode of the sixth transistor being coupled to the third node, a second electrode of the sixth transistor being coupled to the fourth node, and a gate electrode of the sixth transistor being coupled to a fourth input terminal;
a driving transistor, a first electrode of the driving transistor being coupled to the first node, a second electrode of the driving transistor being coupled to the third node, and a gate electrode of the driving transistor being coupled to the second node;
a first capacitor, a first electrode of the first capacitor being coupled to a second power supply voltage, and a second electrode of the first capacitor being coupled to the second node; and
a fifth transistor, a first electrode of the fifth transistor being coupled to the second power supply voltage, a second electrode of the fifth transistor being coupled to the first node, and a gate electrode of the fifth transistor being coupled to a third input terminal;
wherein the third input terminal is coupled to a third control signal lead, and is maintained at a low level in both a triggering sub-stage and a maintaining sub-stage of a capacitor resetting stage,
wherein the third control signal lead jumps to a high level before a data writing stage following the capacitor resetting stage and jumps to the low level during a light emitting stage after the data writing stage.