| CPC G09G 3/32 (2013.01) [G09G 2320/0233 (2013.01); G09G 2320/0247 (2013.01); G09G 2330/021 (2013.01)] | 19 Claims |

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1. A circuit component, comprising:
an input end and at least one signal channel end, wherein the input end is configured to receive an ith image signal at a first frequency, and i is a positive integer; and
the circuit component further comprises a logic control circuit configured to generate an ith drive control signal based on the ith image signal and repeatedly send the ith drive control signal at a second frequency, wherein the ith drive control signal is configured to control a current flowing through the at least one signal channel end;
wherein the logic control circuit comprises:
a counter circuit configured to count a first number of repeated sending of the ith drive control signal;
a buffer circuit configured to store an image signal; and
a first processing circuit coupled with the input end, the counter circuit and the buffer circuit; wherein
the first processing circuit is configured to: judge whether the first number reaches a set number and whether the input end receives an (i+1)th image signal, and store the (i+1)th image signal to the buffer circuit in response to the first number being less than the set number and the input end receiving the (i+1)th image signal.
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