US 12,456,043 B2
Two-dimensional mesh for compute-in-memory accelerator architecture
Shubham Jain, Elmsford, NY (US); HsinYu Tsai, San Jose, CA (US); Geoffrey Burr, Cupertino, CA (US); Milos Stanisavljevic, Adliswil (CH); and Pritish Narayanan, San Jose, CA (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Mar. 31, 2022, as Appl. No. 17/657,431.
Prior Publication US 2023/0316060 A1, Oct. 5, 2023
Int. Cl. G06N 3/065 (2023.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06N 3/065 (2023.01) [G06F 9/3001 (2013.01); G06F 9/30036 (2013.01); G06F 9/3877 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A microelectronic structure, comprising:
a first compute in-memory (CIM) analog tile configured to store a matrix of weight operands that produce a vector of outputs from a vector of inputs, wherein the first CIM analog tile comprises a first microcontroller configured to execute instructions and perform in-memory operations; and
a first compute core communicatively coupled to the first CIM analog tile, wherein the first compute core comprises a second microcontroller configured to execute instructions.