US 12,456,040 B2
Compute in memory three-dimensional non-volatile NAND memory for neural networks with weight and input level expansions
Yanli Zhang, San Jose, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Sandisk Technologies, Inc., Milpitas, CA (US)
Filed on Jun. 9, 2021, as Appl. No. 17/343,240.
Prior Publication US 2022/0398439 A1, Dec. 15, 2022
Int. Cl. G11C 11/54 (2006.01); G06F 7/523 (2006.01); G06N 3/04 (2023.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); H01L 25/18 (2023.01)
CPC G06N 3/063 (2013.01) [G06F 7/523 (2013.01); G06N 3/04 (2013.01); G06N 3/08 (2013.01); G11C 11/54 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 25/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-volatile memory device, comprising:
a control circuit configured to connect to a plurality non-volatile memory cells that are part of an array of memory cells having a NAND architecture, each of the memory cells connected to a first word line and connected between a source line and one of one or more bit lines, a first set of a plurality of the non-volatile memory cells connected to a first of the bit lines and configured to store a multi-bit weight value for a layer of a neural network encoded as a first set of weight components programmed into the first set of memory cells, each of the first set of weight components including one of a plurality of threshold voltage values, the control circuit configured to:
receive a first, multi-bit input value for the layer of the neural network;
encode the first input value as a first set of one or more input voltages, each of the input voltages being one of a plurality of input voltage levels;
apply a first of the first set of input voltages to the first bit line;
concurrently with applying the first of the first set of input voltages to the first bit line, bias the first word line to a read voltage, the read voltage configured to bias memory cells programmed into at least a first of the plurality of threshold voltage levels to be in a linear region of operation in which the first word line voltage is greater than the first threshold voltage and a drain to source voltage is less that the first word line voltage minus the first threshold voltage; and
measure a resultant current on the source line in response to concurrently biasing the first word line to the read voltage while applying the first of the first set of input voltages to the first bit line.