US 12,456,039 B2
Artificial neural network computation acceleration apparatus for distributed processing, artificial neural network acceleration system using same, and artificial neural network acceleration method therefor
Sang Hun Lee, Yongin-si (KR); Bong Jeong Kim, Seongnam-si (KR); and Joo Hyuk Kim, Seoul (KR)
Assigned to DEEPER-I CO., INC., Seoul (KR)
Appl. No. 17/281,456
Filed by DEEPER-I CO., INC., Seoul (KR)
PCT Filed Jul. 18, 2019, PCT No. PCT/KR2019/008905
§ 371(c)(1), (2) Date Mar. 30, 2021,
PCT Pub. No. WO2020/075957, PCT Pub. Date Apr. 16, 2020.
Claims priority of application No. 10-2018-0119856 (KR), filed on Oct. 8, 2018; and application No. 10-2019-0007723 (KR), filed on Oct. 8, 2018.
Prior Publication US 2022/0004854 A1, Jan. 6, 2022
Int. Cl. G06N 3/063 (2023.01); G06N 3/045 (2023.01); G06N 3/08 (2023.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01)
CPC G06N 3/063 (2013.01) [G06N 3/045 (2023.01); G06N 3/08 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An artificial neural network computation acceleration apparatus for distributed processing a computation of an artificial neural network in which input neurons are hierarchically configured, the apparatus comprising:
an external main memory configured to store input data and synaptic weights for the input neurons;
an internal buffer memory configured to store a synaptic weight and input data required for each cycle of the computation of the artificial neural network among the synaptic weights and the input data stored in the external main memory;
a DMA module configured to directly transmit and receive data to and from the external main memory and the internal buffer memory;
a neural network computation device configured to repeatedly process, for each cycle of the computation of the artificial neural network, a series of sequential steps of reading the synaptic weight and the input data stored in the internal buffer memory so as to perform the computation of the artificial neural network and store a computation result in the external main memory;
a CPU configured to control an operation of storing the input data and the synaptic weights for the input neurons in the external main memory and the internal buffer memory, and an operation of the neural network computation device; and
a general-use communication media block configured to transmit/receive the input data and the synaptic weights for the input neurons and a result of the artificial neural network computation performed by the neural network computation device to/from another acceleration apparatus physically connected regardless of a kind of an integrated circuit,
wherein the general-use communication media block includes a remapping block, a bus control signal matching block, and a monitor block,
wherein the remapping block is configured to remap a width of a bus ID signal and an address specifying a component of a receiver integrated circuit among signals applied from a bus master interface connected to a transmitter integrated circuit,
wherein the bus control signal matching block is configured to analyze a pattern of a bus control signal among the signals applied from the bus master interface and, when a previously applied bus control signal and a subsequently applied bus control signal are the same, configured to reuse the previously applied bus control signal, and
wherein the monitor block is configured to monitor a message applied from a processor interface and interrupt signals applied from an interrupt interface, and transmit the message and the interrupt signals together.