US 12,455,995 B2
Chiplet based artificial intelligence accelerators and configuration methods
Ching-Yu Ko, Ann Arbor, MI (US); Chester Liu, Ann Arbor, MI (US); Mohammed Zidan, Ann Arbor, MI (US); Jacob Botimer, Ann Arbor, MI (US); Timothy Wesley, Ann Arbor, MI (US); Zhengya Zhang, Ann Arbor, MI (US); and Wei Lu, Ann Arbor, MI (US)
Assigned to MemryX Incorporated, Ann Arbor, MI (US)
Filed by MemryX Incorporated, Ann Arbor, MI (US)
Filed on Dec. 10, 2020, as Appl. No. 17/118,381.
Prior Publication US 2022/0188492 A1, Jun. 16, 2022
Int. Cl. G06F 30/331 (2020.01); G06F 18/214 (2023.01); G06F 30/337 (2020.01); G06N 3/08 (2023.01)
CPC G06F 30/331 (2020.01) [G06F 18/2148 (2023.01); G06F 30/337 (2020.01); G06N 3/08 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A processing unit comprising:
a plurality of chiplets including interfaces to communicatively cascade the plurality of chiplets or one or more subsets of the chiplets together, wherein the plurality of chiplets or the subsets of the chiplets are configurable to execute layers or blocks of layers of one or more artificial intelligence models, wherein the plurality of chiplets or the subsets of the chiplets are configurable with parameter data of the one or more artificial intelligence models, and wherein the interfaces are configurable to transfer one or more feature map data streams directly between adjacent cascaded ones of the plurality of chiplets or adjacent cascaded ones of one or more subsets of the chiplets without writing the feature map data streams to an off-chiplet memory.