US 12,455,991 B2
Circuit serialization for parameterized circuit simulation
Hiroshi Horii, Tokyo (JP); Jun Doi, Yokohama (JP); and Christopher James Wood, Long Island City, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 8, 2021, as Appl. No. 17/545,143.
Prior Publication US 2023/0177232 A1, Jun. 8, 2023
Int. Cl. G06F 30/20 (2020.01); G06N 10/40 (2022.01)
CPC G06F 30/20 (2020.01) [G06N 10/40 (2022.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method comprising:
determining, by a system operatively coupled to a processor, a first path of computational nodes and a second path of computational nodes of a parameter tree representing one or more quantum circuits, wherein the parameter tree comprises a plurality of computational nodes, wherein the first path of computational nodes and the second path of computational nodes share one or more computational nodes at the beginning of the first path of computational nodes and the second path of computational nodes, wherein each depth of the parameter tree is labeled with a respective estimated resource consumption of resources of a simulation system to reach the depth, and wherein the resources comprise at least one processor and at least one memory;
creating, by the system, a recovery node representing a shared node between the first path of computational nodes and the second path of computational nodes;
creating, by the system, a serialized path of computational nodes from the first path of computational nodes and the second path of computational nodes based on the respective estimated resource consumption for each depth of the parameter tree, wherein the serialized path of computational nodes eliminates one or more duplicate simulation computations and has a first estimated resource consumption that is less than a second estimated resource consumption of another serialized path created from the first path of computational nodes and the second path of computational nodes that does not eliminate the one or more duplicate simulation computations; and
executing, by the system, using the simulation system, a quantum circuit simulation on the serialized path of computational nodes.