US 12,455,851 B1
Adaptive buffer sharing in multi-core reconfigurable streaming-based architectures
Michele Rossi, Bareggio (IT); Thomas Boesch, Rovio (CH); and Giuseppe Desoli, San Fermo Della Battaglia (IT)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Oct. 4, 2024, as Appl. No. 18/906,697.
Int. Cl. G06F 15/82 (2006.01); G06F 15/78 (2006.01); G06N 3/063 (2023.01)
CPC G06F 15/82 (2013.01) [G06N 3/063 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A hardware accelerator, comprising:
a plurality of functional circuits;
a stream switch; and
a plurality of neural network processing cores coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, wherein the neural network processing cores include at least one sender core having a buffer whose buffer content is sharable with at least one receiver core of the neural network processing cores via at least one of a dedicated output stream link or dedicated virtual channel on a pre-existing output stream link, and wherein the at least one of the dedicated output stream link or dedicated virtual channel is dedicated to sharing the buffer content via the stream switch.