US 12,455,850 B2
Root complex integrated endpoint emulation of a discreet PCIE endpoint
Eng Hun Ooi, Georgetown (MY); Su Wei Lim, Penang (MY); Kuan Hua Tan, Coquitlam (CA); and Prashanth Kalluraya, Sunnyvale, CA (US)
Assigned to SK Hynix NAND Product Solutions Corp.
Filed by SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed on Sep. 28, 2017, as Appl. No. 15/718,110.
Prior Publication US 2019/0095554 A1, Mar. 28, 2019
Int. Cl. G06F 13/20 (2006.01); G06F 13/42 (2006.01); G06F 30/20 (2020.01); G06F 30/33 (2020.01); G06F 30/331 (2020.01); G06F 115/02 (2020.01)
CPC G06F 13/4282 (2013.01) [G06F 30/20 (2020.01); G06F 30/33 (2020.01); G06F 30/331 (2020.01); G06F 2115/02 (2020.01); G06F 2213/0026 (2013.01)] 27 Claims
OG exemplary drawing
 
1. An apparatus implemented at least partially in hardware, the apparatus comprising hardware logic to:
receive a request message to access one or more registers of a hardware device;
determine that the request message includes a request to access one or more Peripheral Component Interconnect Express (PCIe)-specific registers comprising a PCIe Capabilities Register or a PCIe Extended Capabilities register; and
respond to the request message without providing information associated with the one or more PCIe-specific registers.