| CPC G06F 13/1668 (2013.01) [G06F 13/18 (2013.01); G06F 13/409 (2013.01); G06F 13/4243 (2013.01)] | 20 Claims |

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1. A system, comprising:
a high-speed parallel bus comprising:
a first end; and
a second end;
a computing subsystem comprising:
a first bus interface connected to the first end; and
a processor connected to the first end via the first bus interface and configured to:
send, via the first bus interface, a data access command; and
receive, via the first bus interface, data, wherein the first bus interface is configured to:
modulate, through higher-order modulation, the data access command; and
demodulate, through the higher-order modulation, the data; and
a memory subsystem comprising:
a second bus interface connected to the second end; and
a memory component connected to the second bus interface, comprising the data, and configured to:
receive, via the second bus interface and from the computing subsystem, the data access command;
access, according to the data access command, the data; and
send, via the second bus interface and to the computing subsystem, the data,
wherein the second bus interface is configured to:
demodulate, through the higher-order modulation, the data access command; and
modulate, through the higher-order modulation, the data.
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