US 12,455,834 B1
Efficient cache eviction
Bing Han, Shanghai (CN)
Assigned to SAP SE, Walldorf (DE)
Filed by SAP SE, Walldorf (DE)
Filed on Apr. 30, 2024, as Appl. No. 18/650,417.
Int. Cl. G06F 12/12 (2016.01); G06F 12/123 (2016.01)
CPC G06F 12/123 (2013.01) 20 Claims
OG exemplary drawing
 
1. A processor comprising instructions that, when executed by the processor, cause the processor to perform operations comprising:
detecting a request to store a first data record into a cache memory of the processor, the request including the first data record and a corresponding first weight specified for the first data record;
writing the first data record and its corresponding first weight into the cache memory of the processor;
calculating a first score of the first data record based on a first ratio of a first idle time since the first data record was last accessed to the corresponding first weight;
comparing the first score of the first data record to a second score of a second data record stored in the cache memory of the processor, the second score being calculated based on a second ratio of a second idle time since the second data record was last accessed to a corresponding second weight; and
deleting the first data record from the cache memory of the processor based on the comparing of the first score of the first data record to the second score of the second data record stored in the cache memory of the processor.