US 12,455,830 B2
Efficient cache data storage for iterative workloads
Tomasz Bogdan Madajczak, Gdansk (PL)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., 2485 Augustine Drive, CA (US)
Filed on Sep. 29, 2023, as Appl. No. 18/478,735.
Prior Publication US 2025/0110889 A1, Apr. 3, 2025
Int. Cl. G06F 12/10 (2016.01)
CPC G06F 12/10 (2013.01) [G06F 2212/1024 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A method comprising:
processing, by one or more compute circuits, a plurality of data blocks in at least a first processing stage and a second processing stage;
generating, by an updater circuit, a first identifier to identify a storage location storing an initial data block of a first plurality of data blocks;
generating intermediate data by the one or more compute circuits during the first processing stage;
storing the intermediate data in a cache by the one or more compute circuits during the first processing stage, wherein at least a portion of the intermediate data is evicted from the cache during the first processing stage responsive to the cache not having enough available space to store all of the intermediate data;
responsive to detection of an end of the first processing stage, updating, by the updated circuit, the first identifier to cause the one or more compute circuits to begin the second processing stage with portions of the intermediate data in the cache that were not evicted during the first processing stage.