US 12,455,829 B2
Memory device including address table and operating method for memory controller
Chinam Kim, Suwon-si (KR); Taekyeong Ko, Suwon-si (KR); Namhyung Kim, Suwon-si (KR); Dohan Kim, Suwon-si (KR); Byeongnoh Kim, Suwon-si (KR); Bobae Kim, Suwon-si (KR); Changmin Lee, Suwon-si (KR); Kyeongjin Cho, Suwon-si (KR); and Insu Choi, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 28, 2023, as Appl. No. 18/140,974.
Claims priority of application No. 10-2022-0054447 (KR), filed on May 2, 2022.
Prior Publication US 2023/0350809 A1, Nov. 2, 2023
Int. Cl. G06F 12/10 (2016.01)
CPC G06F 12/10 (2013.01) 15 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array; and
a command/address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command/address information, and a second decoding logic circuit configured to decrypt an address table,
wherein the command/address decoder is configured to
decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command,
decrypt data received from the memory controller, after a predefined latency from receipt of the first command, through the second decoding logic circuit to obtain the address table, the address table being configured to store an index mapped with address information of the memory device,
store the address table in the buffer memory,
decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the index of the address table, and
execute the table-based command with respect to an address corresponding to the index based on the index information.