US 12,455,828 B2
Host management of flash memory with shared write buffer
Santhosh Reddy Akavaram, Hyderabad (IN); Chintalapati Bharath Sai Varma, Hyderabad (IN); Prakhar Srivastava, Lucknow (IN); Hung Vuong, Coronado, CA (US); and Ravi Kumar Sepuri, Hyderabad (IN)
Assigned to Qualcomm Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 22, 2023, as Appl. No. 18/472,642.
Prior Publication US 2025/0103499 A1, Mar. 27, 2025
Int. Cl. G06F 12/00 (2006.01); G06F 12/02 (2006.01); G06F 12/084 (2016.01)
CPC G06F 12/084 (2013.01) [G06F 12/0246 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/2022 (2013.01); G06F 2212/601 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A host device comprising:
a host controller interface (HCI) configured to be coupled to a flash memory device and configured to:
receive a notification from the flash memory device that a performance threshold register value has been exceeded, wherein the flash memory device includes a shared write buffer and is configured to use the shared write buffer as a temporary storage for data writes; and
in response to receiving the notification, perform a remedial action that includes:
reassigning a portion of a first logical unit (LU); and
sending a command to the flash memory device to convert the portion of the first LU from a triple-level cell (TLC) memory type to a single-level cell (SLC) memory type.