US 12,455,826 B2
Dynamic caching policies for processing-in-memory
David Andrew Werner, Austin, TX (US); Stuart David Simpson-Biles, Suffolk (GB); and Travis Henry Boraten, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Mar. 29, 2024, as Appl. No. 18/621,319.
Prior Publication US 2025/0307147 A1, Oct. 2, 2025
Int. Cl. G06F 12/0815 (2016.01)
CPC G06F 12/0815 (2013.01) 20 Claims
OG exemplary drawing
 
1. A computing device, comprising:
a memory that includes one or more processing-in-memory units; and
a host processor that includes one or more caches, the host processor configured to:
receive a workload that accesses a page of the memory;
dynamically assign different modes of operation to the page of the memory during different phases of execution of the workload based on whether the workload is to be executed by the host processor, the one or more processing-in-memory units, or the host processor and the one or more processing-in-memory units during the different phases of execution; and
process requests of the workload that access the page of the memory in accordance with the different modes of operation during the different phases of execution, the different modes of operation specifying different caching policies for the page of the memory.