US 12,455,825 B2
Method for supporting cache coherency based on virtual addresses for artificial intelligence processor having large on-chip memory and apparatus for the same
Jin-Ho Han, Daejeon (KR); and Young-Su Kwon, Daejeon (KR)
Assigned to ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, Daejeon (KR)
Filed by ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, Daejeon (KR)
Filed on Nov. 29, 2023, as Appl. No. 18/522,776.
Claims priority of application No. 10-2022-0163064 (KR), filed on Nov. 29, 2022; and application No. 10-2023-0088228 (KR), filed on Jul. 7, 2023.
Prior Publication US 2024/0211401 A1, Jun. 27, 2024
Int. Cl. G06F 12/08 (2016.01); G06F 12/0815 (2016.01); G06F 12/1027 (2016.01)
CPC G06F 12/0815 (2013.01) [G06F 12/1027 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for supporting cache coherency based on virtual addresses, the method comprising:
by an artificial intelligence processor including multiple processor cores, multiple caches, and a bus located between the multiple processor cores and the multiple caches,
setting, among the multiple caches, external memory address areas which do not overlap with each other; and
providing virtual addresses with which the multiple processor cores access the multiple caches,
wherein the external memory address areas respectively correspond to address areas of an external memory located outside the artificial intelligence processor, and
wherein the setting of the external memory address areas is performed by the bus based on memory map information associated with both the multiple caches and the external memory.