US 12,455,824 B2
DRAM cache with stacked, heterogenous tag and data dies
Taeksang Song, San Jose, CA (US); Michael Raymond Miller, Raleigh, NC (US); and Steven C. Woo, Saratoga, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Sep. 5, 2023, as Appl. No. 18/242,344.
Claims priority of provisional application 63/463,260, filed on May 1, 2023.
Claims priority of provisional application 63/405,408, filed on Sep. 10, 2022.
Prior Publication US 2024/0086325 A1, Mar. 14, 2024
Int. Cl. G06F 12/08 (2016.01); G06F 12/0815 (2016.01); G06F 12/123 (2016.01)
CPC G06F 12/0815 (2013.01) [G06F 12/123 (2013.01); G06F 2212/305 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A cache memory comprising:
a first dynamic random access memory (DRAM) die having a first DRAM array to store address tags and circuitry to generate a cache hit/miss result in response to a cache access request by comparing a search tag supplied with the cache access request with the address tags stored within the first DRAM array;
a second DRAM die coupled in a stacked-die configuration with the first DRAM die and having a second DRAM array to store cache lines corresponding to the address tags;
an interface to receive the cache access request from a processor die that is coupled in a stacked-die configuration with the first DRAM die and the second DRAM die, the interface including a dedicated hit/miss bus: and
circuitry to output one or more signals representative of the hit/miss result from the first DRAM die to the processor die via the dedicated hit/miss bus.