US 12,455,823 B2
Super-temporal cache replacement policy
Gabriel Hsiuwei Loh, Bellevue, WA (US); Joseph Lee Greathouse, Austin, TX (US); William Louie Walker, Fort Collins, CO (US); and Paul James Moyer, Fort Collins, CO (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 9, 2023, as Appl. No. 18/332,112.
Prior Publication US 2024/0411692 A1, Dec. 12, 2024
Int. Cl. G06F 12/0802 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 2212/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a cache that includes a cacheline having a bit indicating whether the cacheline is protected by a computational task or unprotected, wherein protected cachelines are eligible for eviction;
guiding logic to guide decisions of a cache replacement policy by favoring eviction of unprotected cachelines over eviction of the protected cachelines; and
a controller to select a cacheline of the cache to evict responsive to a cache miss based on the cache replacement policy and the guiding logic.