US 12,455,821 B2
Memory access tracing
Ankit Patel, Folsom, CA (US); Lidia Warnes, Roseville, CA (US); Donald L. Faw, Hillsboro, OR (US); Bassam N. Coury, Portland, OR (US); Douglas Carrigan, Chandler, AZ (US); Hugh Wilkinson, Newton, MA (US); Ananthan Ayyasamy, Beaverton, OR (US); and Michael F. Fallon, Wellesley, MA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 24, 2022, as Appl. No. 17/849,387.
Claims priority of provisional application 63/252,018, filed on Oct. 4, 2021.
Prior Publication US 2022/0334963 A1, Oct. 20, 2022
Int. Cl. G06F 12/06 (2006.01); G06F 12/0868 (2016.01); G06F 12/0877 (2016.01)
CPC G06F 12/0646 (2013.01) [G06F 12/0868 (2013.01); G06F 12/0877 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a hardware interconnect to communicatively couple at least one device and a memory via a memory controller and
circuitry, when operational, configured to:
trace requests for memory access to the memory from multiple requesters and
store records of the memory accesses to the memory based on a configuration, wherein:
the configuration is to specify a duration of memory access capture for the multiple requesters, requester identifier to track memory accesses, physical address ranges, or read or write access type,
the multiple requesters are associated with the at least one device,
the records of the memory accesses comprise a requester identifier and two or more of: event type, time value of elapsed duration since storage of data in a buffer, or address,
the memory comprises a memory pool, and
the memory pool comprises at least one dual inline memory module (DIMM).