| CPC G06F 12/0246 (2013.01) [G11C 29/12 (2013.01)] | 20 Claims |

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1. A nonvolatile memory device comprising:
a memory cell array including a plurality of memory planes, each of the plurality of memory planes including memory blocks, each of the memory blocks including memory cells; and
a control circuit configured to control an operation of the memory cell array in units of super blocks, the super blocks including memory blocks included in different memory planes,
wherein a first memory block is included in a first super block of the super blocks and a first memory plane of the plurality of memory planes, and is configured to store first sensitive data that is required while the nonvolatile memory device is operating,
wherein a second memory block is included in the first super block and a second memory plane of the plurality of memory planes different from the first memory plane, and is configured to store replicated data identical to the first sensitive data, and
wherein a third memory block is included in the first super block and a third memory plane of the plurality of memory planes different from the first and second memory planes, and is configured to store second sensitive data that is required while the nonvolatile memory device is operating and is obtained during a first manufacturing process for the nonvolatile memory device.
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